Many portable electronic devices, such as cameras, cellular telephones, Personal Digital Assistants (PDAs), MP3 players, computers, and other devices include a semiconductor (e.g., complementary metal-oxide-semiconductor; CMOS) imaging device for capturing images using an array of pixels. FIG. 1 depicts an imaging device 100 that includes an array 102 of pixels 104 and a timing and control circuit 106. The timing and control circuit 106 provides timing and control signals for enabling the reading out of signals from pixels 104 of the pixel array 102 in a manner commonly known to those skilled in the art. Although one pixel 104 is illustrated, the pixel array 102 has dimensions of Y rows by X columns of pixels 104, with the size of the pixel array 102 depending on the application.
Signals from the imaging device 100 are typically read out a row at a time using a column parallel readout architecture. The timing and control circuit 106 selects a particular row of pixels in the pixel array 102 by controlling the operation of a row addressing circuit 108 and row drivers 110. Signals stored in the selected row of pixels are provided to a readout circuit 112 in the manner described above. The signals are read twice from each of the columns and then read out sequentially or in parallel using a column addressing circuit 114. The pixel signals (Vrst, Vsig) corresponding to a pixel reset signal and an pixel image signal are provided as outputs of the readout circuit 112, and are typically subtracted by a differential amplifier 116 in a correlated double sampling (CDS) operation and the result digitized by an analog to digital converter (ADC) 118 to provide a digital pixel signal represent an image captured by pixel array 102 for processing by an image processing circuit 120.
Pixel values are read out as tiny voltages, on the order of microvolts per electron. Those voltages are passed to the ADC 118 for conversion into a digital pixel value. FIG. 2 depicts a prior art ADC 200 known as a ramp ADC. Vin is the analog input voltage and Dn through D0 are multiple bit digital outputs (eight output bits are illustrated). A counter 202 starts counting when an analog input voltage is to be converted. The counter supplies a digital counter value to a digital to analog converter 204, which generates a comparison voltage level at a comparator 206. As the counter 202 increases, the comparison voltage incrementally increases for comparison with the analog input voltage. Once the comparison voltage exceeds the analog input voltage, the counter 202 ends with the end value representing the multiple bit digital output of the analog input voltage. An ADC such as ADC utilize up to 2^n−1 clock cycles to convert each analog voltage sample. Thus, for an 8-bit ADC, it take up to 255 clock cycles to convert a single sample. For a 16-bit ADC it would take up to 65,535 clock cycles to convert one sample.
FIG. 3 depicts another prior art ADC 300 known as a successive approximation register (SAR) ADC. Vin is the analog input and Dn through D0 are the multiple bit digital outputs. A SAR 302 supplies a digital value to a digital to analog converter 304, which generates a comparison voltage level at a comparator 306. A controller 308 sets the SAR 302 and monitors the comparator 306 to identify the multiple bit digital output one bit at a time from the most significant bit (MSB) to the least significant bit (LSB). A buffer 310 stores each bit of the multiple bit digital output so the digital data remains available while the ADC 300 is processing the next sample of the analog input voltage.
In operation, the SAR 302 initially supplies to the DAC 304 a “1” in the MSB position and “0”s in the remaining positions. If the input voltage is greater than the comparison voltage level, a “1” is stored for the MSB and the ADC 300 proceeds with the MSB and the next MSB set to “1.” If the input voltage is less than the comparison voltage level, a “0” is stored for the MSB and the ADC 300 proceeds with the MSB set to “0” and the next MSB set to “1.” The ADC 300 proceeds until all bits of the multiple bit digital output are determined. Thus, the ADC 300 is able to find the correct digital value for the analog input voltage in n clock cycles, where n is the number of bits in the multiple bit digital output. For an 8-bit ADC 300, the digital value for each sample can be found in up to eight clock cycles (compared to 255 for ADC 200 (FIG. 2)), and for a 16-bit ADC the digital value for each sample can be found in up to 16 clock cycles (compared to 65,535 for ADC 200 (FIG. 2)).
Noise is an important factor in the design of imaging devices. Noise may result from many of the operations performed during the capture and digitization of an image, both uncorrelated, random noise and periodic noise. Low frequency noise is minimized by CDS, but CDS increases temporal noise. Multisampling is one known technique for reducing low and high frequency noise. Known multisampling techniques, however, are difficult to commercially implement due to frame rate and silicon area limitations.